A) Field of the Invention
The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device manufacturing method with an inspection for hole opening for via holes to be formed through an insulating film on a wiring layer, and to semiconductor devices manufactured by such a method.
B) Description of the Related Art
Several inspection methods for hole opening are known for inspecting whether a via hole formed through an interlayer insulating film reaches the surface of the underlying layer of the interlayer insulating film.
FIG. 12A is a cross sectional view showing a peripheral area of a via hole to be inspected by the inspection method for hole opening disclosed in JP-A-60-109240. On an underlying interlayer insulating film 500, a wiring line 501 is formed. An upper interlayer insulating film 502 formed on the interlayer insulating film 500 covers the wiring line 501. A via hole 503 is formed through the interlayer insulating film 502. The via hole 503 is disposed so that the edge of the wiring line 501 passes through the bottom area of the via hole 503, as viewed along a line parallel to the normal to the substrate surface.
If the via hole 503 reaches the wiring line 501, a step formed by the wiring line 501 can be observed when the bottom of the via hole is observed with a scanning electron microscope (SEM). If the via hole 503 does not reach the wiring line 501, a step by the wiring line cannot be observed.
An inspection for opening of the via hole 503 can therefore be made relying upon whether the step by the wiring line 501 can be observed.
As shown in FIG. 12B, if the edge of a wiring line 507 to be formed on an interlayer insulating film 505 having a via hole 506 is disposed in the opening of the via hole, it is possible to detect an alignment shift between the layer formed with the via hole 506 and the layer disposed with the wiring line, by observing the step on the bottom of the via hole 506.
FIGS. 13A and 13B are cross sectional views showing peripheral areas of via holes to be inspected by the inspection method for hole opening disclosed in JP-A-4-12531.
As shown in FIG. 13A, a wiring line 511 is disposed on an underlying interlayer insulating film 510. An upper interlayer insulating film 512 disposed on the interlayer insulating film 510 covers the wiring line 511. The region of the interlayer insulating film 512 above the wiring line 511 is swelled, and the interlayer insulating film 512 becomes thicker near in the central area of the wiring line 511. Therefore, as a via hole 513 is formed in an area corresponding to the wiring line 511, residues 514 are likely to be left on the wiring line 511. The left residues 514 make it difficult to detect a step of the wiring line 511.
As shown in FIG. 13B, if two wiring lines 511 are juxtaposed, the upper surface of an interlayer insulating film 512 between the two wiring lines 511 can be made generally flat. If a via hole overriding at least one of the two wiring lines is formed in the interlayer insulating film 512, residues are not left on the wiring lines 511 and a step of the wiring line or lines 511 can be detected easily.
FIG. 14 is a cross sectional view showing a peripheral area of via holes to be inspected by the inspection method for hole opening disclosed in JP-A-11-297777. On the surface of a semiconductor substrate 520, an interlayer insulating film 521 is formed on which a wiring line 522 is formed. The wiring line 522 is electrically connected to the semiconductor substrate 520 via a via hole 523 formed through the interlayer insulating film 521.
An upper interlayer insulating film 524 formed on the interlayer insulating film 521 covers the wiring line 522. Via holes 525 are formed in the interlayer insulating film 524 to expose the partial upper surfaces of the wiring line 522. The bottom of each via hole 525 observed with a SEM is bright if the wiring line 522 is exposed, and dark if the via hole 525 does not reach the wiring line 522.
Even if the wiring line 522 is exposed on the bottom of the via hole 525, the brightness of the bottom of the via hole lowers if electrons are accumulated in the wiring line 522, and this case cannot be discriminated from the case that the via hole 525 does not reach the wiring line 522. The structure that the wiring line 522 is connected to the semiconductor substrate 520 as shown in FIG. 14 can prevent accumulation of electrons in the wiring line 522.
As compared to a conventional method of forming a wiring line by patterning a metal layer through reactive ion etching (RIE), a damascene method can satisfy more easily high integration requirements of semiconductor integrated circuit devices and can expect a reduction in the number of processes. The damascene method has therefore drawn attention and is suitable for forming a copper wiring with a lowered wiring resistance.
FIG. 15A is a cross sectional view showing a peripheral area of a via hole during a process of forming a copper wiring by a damascene method. In a wiring groove formed in a surface layer of an underlying interlayer insulating film 530, a copper wiring line 532 is embedded. In order to prevent copper diffusion, the inner surface of the wiring groove is covered with a barrier metal layer 531 of tantalum (Ta) or the like.
On the interlayer insulating film 530, a silicon nitride (SiN) film 533, a silicon oxide (SiO2) film 534, a low dielectric constant insulating film 535, an SiO2 film 536, and an SiN film 537 are laminated in this order from the bottom. This lamination structure is formed with a via hole 538 which exposes a partial upper surface of the copper wiring line 532. A wiring groove 539 is formed overlapping the via hole 538, and reaches the bottom of the low dielectric constant insulating film 535.
FIG. 15B shows a SEM photograph showing the peripheral area of the via hole 538. Since the bottom of the via hole 538 is dark, it is not possible to judge whether the copper wiring line 532 is exposed.
FIG. 15C is a cross sectional view showing the peripheral area of a via hole 538A wherein the via hole 538A is slightly shifted from a copper wiring line 532 so that the edge of the copper wiring line 532 passes through the bottom area of the via hole 538A. The via hole 538A is formed by etching the lamination structure to the bottom of the SiO2 film 534 by using the SiN film 533 as an etching stopper film and thereafter removing the SiN film 533 exposed on the bottom of the via hole.
The etching conditions for the SiN film 533 are usually set so that the interlayer insulating film 530 and copper wiring line 532 are scarcely etched. Therefore, a step corresponding to the edge of the copper wiring line 532 is not formed.
FIG. 15D is a SEM photograph showing the peripheral area of the via hole 538A. Almost the whole area of the bottom of the via hole 538A is observed dark and the boundary between the copper wiring line 532 and interlayer insulating film 503 cannot be detected. This is because there is no step as opposed to the conventional example shown in FIG. 12A.
The inspection for hole opening without utilizing a step is possible for the conventional case shown in FIG. 14. However, as a diameter of the via hole 525 becomes small, a difference between darkness and brightness of the exposed and unexposed wiring lines 522 becomes small so that highly reliable inspection for hole opening is not possible.